The present invention pertains to highly reliable, real time duplex processor systems and more particularly to synchronization and control of duplex processors via active/standby serial communication links connected between the duplex processors and a remote control system.
In processor systems which require a high degree of reliability, these systems are often designed with duplex processors and duplex busing between the processors and associated peripheral devices such as taught by Applicant's U.S. Pat. No. 4,736,339, issued Apr. 5, 1988, and titled, CIRCUIT FOR SIMPLEX I/O TERMINAL CONTROL BY DUPLEX PROCESSORS. This circuit teaches a means of controlling and connecting simplex peripheral devices, such as teletype terminals to a duplex processor system. These systems usually require some sort of configuration control circuitry. This control circuitry usually takes the form of a third party processor. The third party processor may be a hard wired logic or a software controlled processor.
Each of the duplex processors in such a system is step-lock synchronized with the other processor of the pair. The third party processor then monitors the buses of the two duplex processors to determine that they are executing the same instruction at the same time. Or in cases in which one processor controls both copies of the system buses, the third party processor will switch between the two duplex processors according to a determination by the third processor of which processor is correctly operating. For a detection of lack of synchronization or faults, the third party processor controls the switching of the duplex processors to the bus configuration of the system and removal of the faulty processor.
Such configuration control circuits as third party processors are generally complex. These designs are difficult to implement, debug, maintain and control. In addition, a fault in the third party processor generally results in a total system outage. Real time processor systems cannot tolerate total system outages.